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🏛️ 11.Sep.2026
🇰🇷🇫🇮 On September 11 and 12, we hosted the 2026 Korea-Finland Chip Design Symposium at Aalto University, the second edition following last year’s inaugural event!
Supported by the Ministry of Foreign Affairs, Republic of Korea, the symposium once again brought together researchers and industry experts from 🇰🇷 Korea, 🇫🇮 Finland, 🇨🇭 Switzerland, 🇺🇸 United States, and 🇦🇪 UAE, covering integrated circuit design from quantum computing and AI to wireless and sensing systems.
Many thanks to all invited speakers, the Embassy of the Republic of Korea in Finland, and our volunteer students! The full program is available on the Events page.
✈️ 13.Aug.2026
Our PhD student Soujanya Bhowmick has been awarded a 2026 IEEE Circuits and Systems Student Travel Grant!
The grant covers up to $400 for reimbursement for Soujanya’s travel to IEEE AICAS 2026.
Congrats, Soujanya!
📚 29.Jun.2026
The first algorithm paper from our group has been accepted to IEEE AICAS in Ha Long Bay, Vietnam 🇻🇳!
This work is closely tied to our HolistIC project on Analog-Digital-Algorithm co-design. Big thanks to our collaborators:
- Sangyeob Kim, Yonsei University, South Korea 🇰🇷
- Qinyu Chen, Leiden University, Netherlands 🇳🇱
- Chang Gao, TU Delft, Netherlands 🇳🇱
Congrats, Soujanya!
🎉 11.Jun.2026
Kwantae has been awarded the Academy Research Fellowship (ranked 1st in the review panel) by the Research Council of Finland (RCF)! The project is funded with €1M in total over the next 4 years.
HolistIC: Analog-Digital-Algorithm Co-Optimized System-on-Chip for Intelligent Audio IoT Sensors
Our group aims to develop a next-generation audio chip that unifies sensor interface, data processing, and inference through holistic co-design. This project will be carried out in collaboration with the following research groups:
- Sangyeob Kim, Yonsei University, South Korea 🇰🇷
- Komail Badami, CSEM Zurich, Switzerland 🇨🇭
- Martin Andraud, UCLouvain, Belgium 🇧🇪
We sincerely thank the Research Council of Finland for the funding decision and the reviewers for their valuable feedback!
Stay tuned for updates from our group!
21.Mar.2026
We open-source cdl_gen, a Python-to-schematic generator for Cadence Virtuoso.
Claude successfully generates a 4-bit cap DAC with 2% mismatch with cdl_gen.
We hope cdl_gen can be helpful for analog/mixed-signal designers!
🎉 20.Feb.2026
The FENNEC project that Kwantae contributed has received the Demo Session Award at the IEEE ISSCC!
