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News
21.Mar.2026
We open-source cdl_gen, a Python-to-schematic generator for Cadence Virtuoso.
Claude successfully generates a 4-bit cap DAC with 2% mismatch with cdl_gen.
We hope cdl_gen can be helpful for analog/mixed-signal designers!
🎉 20.Feb.2026
The FENNEC project that Kwantae contributed has received the Demo Session Award at the IEEE ISSCC!
